The present invention relates to an error correction circuit and method. In particular, a system and method are provided for an error correction circuit used in association with a dynamic random access memory (DRAM) system.
Memory systems, such as DRAM systems, have large memory arrays with large numbers of individual memory cells. During fabrication of the memory arrays, or in subsequent packaging of the memory, it is possible for single cell failures to be introduced in the memory. In some cases, introduction of such failures can result in the need to scrap the entire package afterwards.
Consequently, many memory systems utilize error correction circuits (ETC.) to compensate for single cell failures in memory arrays. ECC generate parity codes and utilize a parity memory to detect, and in some cases correct, errors or failures in memory cells. In some cases, such ECC are built directly onto a memory chip in order to achieve superior quality for a customer.
Typically, memory chips are tested after fabrication and assembly to determine whether they are operating properly. In cases where ECC are integrated into the memory chip, testing of these memory systems can become cumbersome. If the testing must also test whether the ECC has corrected errors or failures in memory cells, extra testing time and processing resources are sometimes needed.
For these and other reasons, there is a need for the present invention.